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Enhanced coupling effects in vertical double-gate FinFETs

Authors :
Sorin Cristoloveanu
Kerem Akarvardar
I. Ionica
Jong-Hyun Lee
Fanyu Liu
S.-J. Chang
Maryline Bawedin
Jung-Hee Lee
Yufeng Guo
Department of Electrical Engineering [Yale University]
Yale University [New Haven]
Institut d’Electronique et des Systèmes (IES)
Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)
Micro électronique, Composants, Systèmes, Efficacité Energétique (M@CSEE)
Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)
Nanjing University of Posts and Telecommunications [Nanjing] (NJUPT)
Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC)
Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)
Kyungpook National University [Daegu]
ANR-11-JS03-0001,AMNESIA,Dispositifs Mémoires Nanométriques Innovants pour Applications Ultra Basse Consommation(2011)
European Project: 257375,ICT,FP7-ICT-2009-5,NANOFUNCTION(2010)
Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)
Kyungpook National University [Daegu] (KNU)
Source :
Solid-State Electronics, Solid-State Electronics, Elsevier, 2014, 97, pp.88-98. ⟨10.1016/j.sse.2014.04.024⟩, Solid-State Electronics, 2014, 97, pp.88-98. ⟨10.1016/j.sse.2014.04.024⟩
Publication Year :
2014
Publisher :
HAL CCSD, 2014.

Abstract

International audience; Vertical double-gate (DG) FinFETs fabricated on SOI wafers show good gate control, reasonable threshold voltage and high carrier mobility despite the absence of the top-gate. The 3D coupling effect between the two lateral-gates and the back-gate is investigated based on experimental and simulation results. We compare DG and triple-gate FinFETs with various fin widths. Front-channel characteristics are easily tuned by applied bias at the back-gate if the fin is not too narrow. We highlight that vertical DG FinFET is more appropriate device for dynamic threshold voltage adjustment than triple-gate FinFET. An analytical model is proposed to quantify the coupling effect in DG FinFET by solving 2D Poisson equation. The body potential profile and coupling effect are modeled. A very good agreement is obtained between experiments, 3D simulations and the proposed model.

Details

Language :
English
ISSN :
00381101
Database :
OpenAIRE
Journal :
Solid-State Electronics, Solid-State Electronics, Elsevier, 2014, 97, pp.88-98. ⟨10.1016/j.sse.2014.04.024⟩, Solid-State Electronics, 2014, 97, pp.88-98. ⟨10.1016/j.sse.2014.04.024⟩
Accession number :
edsair.doi.dedup.....f70f9d2a2f5a5d5a2f49fd7cc1cb2ae9
Full Text :
https://doi.org/10.1016/j.sse.2014.04.024⟩