HDL based implementation of a node of hierarchical temporal memory

The main intention of this thesis is to give the basic information about the implementation of a node of one of the neural network algorithms. The main purpose of this thesis is to design, implement and analyze the node of the HTM (Hierarchical Temporal Memory) algorithm suggested by Jeff Hawkins [1]. In this document, a design implementation of HTM algorithm node based on Verilog hardware description language and MATLAB programming language is given. The node of HTM algorithm is implemented using Xilinx Spartan-3e FPGA (Field Programmable Gate Array) kit. The simulation results obtained with Xilinx ISE (Integrated Software Environment) 10.1 software are also provided.