Evaluation of Cryogenic Readout Circuits with GaAs JFETs for Far-Infrared Detectors

The characteristics of gallium arsenide junction field-effect transistors (GaAs JFETs)and the performance of cryogenic readout circuits using GaAs JFETs for two-dimensional far-infrared arrays are evaluated at cryogenic temperature. We fabricated the GaAs JFETs withvarious gate sizes ranging from W/L = 5μm/0.5μm to 200μm/200μm to systematically measuretheir static characteristics and low-frequency noise spectra. We found that the low-frequency noisevoltage depends on the device size in the saturation region of GaAs JFETs at 4.2 K, and the powerdensity of the noise voltage is inversely proportional to the gate area. These findings allowed usto determine the Hooge parameter of the GaAs JFET at 4.2 K to be 4×10-5, assuming that thecarrier mobility is 1.5×10+3 cm2/Vs. On the other hand, we did not find the obvious correlationbetween the low-frequency noise and gate size in the ohmic region of GaAs JFETs. Based on thesemeasurements for GaAs JFETs, we fabricated and tested a dual GaAs JFET, a source-follower-per-detector (SFD) circuit, and a 20×3 channel SFD circuit array. The Common-Mode-Rejection-Ratio(CMRR) of the dual GaAs JFET with W/L = 50μm/20μm at 4.2 K was determined to be 40-60dB under small power dissipation. The performance of SFD circuits and the 20×3 channel SFDarrays for two-dimensional far-infrared Ge:Ga detector readouts are currently being evaluated.
資料番号: SA4618377000