Characterisation Methods and Industry-compatible Manufacturing Processes for thin multi-crystalline Silicon Solar Cells

The cumulative output of produced solar cells reached the 1 Gigawatt level in 2002. Assuming an annual growth rate of 40 %, as was seen in 2003, this will be the total produced power in 2004 alone. The consequence is a definite decline of Wattpeak-prices of solar cells. Simultaneously, the importance of the worldwide shortage of available silicon material is increasing. Therefore, the potential for cost reduction and material savings will play a major role in the future of the solar cell industry.In addition to wafer area enlargement this demand could be filled by a reduction in material thickness. The number of wafers sawed from silicon blocks could be increased by 40 % by using 200 µm wafer thicknesses instead of 330 µm. A reduction in wafer thickness requires appropriate process adaptations. The conception, development and evaluation of a manufacturing sequence suitable for thinner wafers form the essence of the work in this thesis.Reducing wafer thickness also reduces mechanical stability with a corresponding increase in the breakage rate in industrial production and therefore a production loss. To understand the reasons behind this material weakness, the mechanical properties of silicon wafers and the impact of different process steps on the material were investigated in detail in this thesis.The alkaline etch process was found to increase the mechanical stability by 10 %, and high temperature steps were found to lead to a stability decrease. For damaged material, crack propagation after diffusion was found. To sort out cracked material, crack recognition methods are necessary, four are introduced in this work and evaluated. Two of these methods were enhanced for solar cells. The first is a mechanical stability test (Twist-Test), which showed a reduction in the breakage rate of 75 % when used in an industrial investigation.The second crack detection method investigated was Laser-Scanning-Vibrometry, which was enhanced for crack recognition on solar cells. This method is based on a modal-analysis of wafers that are excited to mechanical swinging by acoustic waves. By comparing the resonance frequencies, cracks in silicon wafers were detected. In order to increase the recognition rate, different pattern recognition methods were tested using Finite-Element -simulations. The general capability for crack detection on silicon wafers was demonstrated with these results.In addition to a decrease in stability, a reduction in cell thickness leads to strong bowing after metallization of solar cells. This could exceed the limits required for module fabrication. The reasons for this bowing and possibilities for its reduction are discussed in detail in this work. A fitting formula for bow-calculations is described. By reducing the amount of printed paste, the bowing was reduced by up to 35 % while maintaining cell efficiency. Aluminium concentration optimisations resulted in 60 % less bowing. Further reductions in the bow were realised by varying firing conditions, front grid designs, paste compositions and by special rear side screen designs. With these results, processing of wafers down to 160 µm thickness, sized 12.5*12.5 cm² with low bowing was demonstrated. The best cell efficiency of a 180 µm thick solar cell was 16 %.Reducing the cell thickness has a direct effect on efficiency. The reduced thickness results in a reduced short circuit current due to the reduced light absorption and may result in a reduced open circuit voltage due to the increased influence of rear side recombination. To understand the influence of reducing the thickness on cell parameters, simulations and experiments on neighbouring material of varying thicknesses were done. The experiments showed a 7 mV reduction in open circuit voltage and 0.7 mA/cm² reduction in short circuit current with a reduction in wafer thicknesses from 305 µm to 120 µm. For cases where the diffusion length was greater than the cell thicknesses, this effect could be explained by rear-side recombination effects. In order to lower front-side reflection, novel plasma texturing was integrated into the industrial process developed for thin wafers. Following several optimisations, an increase in short circuit current of 0.9 mA/cm² and an increase in open circuit voltage of 2-3 mV were demonstrated.The work in this thesis describes the physical boundary conditions for thin silicon wafer processing and demonstrates methods to reach high cell efficiency with modified industrial process sequences.