Design of a low-voltage input-output rail-to-rail CMOS buffer

The objective of this project is to design a low-voltage rail-to-rail input/output CMOS buffer, which is able to work under a supply voltage of 1.8V typical and remain in operation even at l.2V or lower in the worst case for use in bond pad designs. The circuit is designed and simulated using Cadence Software. The process used is O.18um N-well CMOS single-poly six-metal layers. A low-voltage rail-to-rail input/output buffer is proposed, which combines a constant-gm rail-to-rail input stage and a compact rail-to-rail output stage with Class-AB configuration. The buffer can work effectively when the supply voltage change form 1.8V to 1.2V. The rail-to-rail operation has been achieved for input and output. The positive slew rate is 2.39V/us, and the negative slew rate is -2.32V/us. The following report demonstrates the design course of this project. The overall specifications achieved by this buffer are also presented at the end of this report. Master of Science (Integrated Circuit Design)