TCP/IP Control Server for a Multi-Drop Test Bench Network

This thesis describes the design, construction and verification process in full for the test server portion of the second generation of an automated testing network. The system was built for, and with, AMD/ATI of Markham, Ontario and will be used to test large batches of their graphics processing units (GPU's). The final test system has the capability to simultaneously test and control several parameters on a large number of test nodes. The TCP/IP Control Server for a Multi-Drop Test Bench Network was designed to test and control a network of 256 test nodes over an RS-485 network. The contents of this thesis will describe the test server hardware in full, while the test nodes are described in Stephen Fox's thesis. The test server consists of an Ethernet-enable MCU, an Altera Cyclone II FPGA and a custom RS-485 transceiver board used to communicate with the test nodes.