Flexible Low-Area Hardware Architectures for Packet Processing in Software-Defined Networks

Computer networks have changed radically in the last 10 years. Advances in computer networks and emergence of new network protocols require more flexibility and programmability in forwarding devices such as switches and routers. The main components of these devices are the control and data plane. The former instructs functionality and the latter just executes the dictated functionality. In the traditional philosophy for designing forwarding devices, the control and data plane were tightly coupled. With increase in the number and complexity of network protocols, this design principle proved to be inefficient. Software Defined Networking (SDN) breaks this tight coupling of the control and data plane. Under this network architecture, a central controller installs forwarding rules on the tables in forwarding devices. SDN-based forwarding devices only contain the data plane and the interface for communicating with the control plane. By matching the value of header fields against the installed rules, the data plane executes the corresponding actions. Research on SDN is done on the control and data planes as well as and the interface making their communication possible. In this dissertation, the focus is on the programmable data plane. It is the enabling component for protocol-independent packet processing. The most notable hardware architecture for programmable data plane is Reconfigurable Match Tables (RMT). Despite its capabilities, there are a number of shortcomings associated with it that make it unnecessarily complex, limit its flexibility and use the memory resources inefficiently. In response to these shortcomings, a new architecture has been designed and implemented. The packet parser in this new architecture does not employ Ternary Content Addressable Memory (TCAM). As a result, it reduces the area of memories required for Match-Action packet parsing by 50%. The area saving is used for providing packet preprocessing functionality in the packet parser. The crossbar alternatives for search key generation and action input selection have been explored and the most area-efficient alternatives has been selected. Yet another packet parser is designed whose supported throughput is 10 times that of RMT parser whereas the area increase factor is less than 2. Finally, a packet processing pipeline has been designed with enhanced level of flexibility and functionality. Despite the enhancements, it has 31% less area compared to the RMT pipeline.