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A combinatorial approach to X-tolerant compaction circuits
- Source :
- IEEE Transactions on Information Theory, 56 (2010) 3196-3206
- Publication Year :
- 2015
-
Abstract
- Test response compaction for integrated circuits (ICs) with scan-based design-for-testability (DFT) support in the presence of unknown logic values (Xs) is investigated from a combinatorial viewpoint. The theoretical foundations of X-codes, employed in an X-tolerant compaction technique called X-compact, are examined. Through the formulation of a combinatorial model of X-compact, novel design techniques are developed for X-codes to detect a specified maximum number of errors in the presence of a specified maximum number of unknown logic values, while requiring only small fan-out. The special class of X-codes that results leads to an avoidance problem for configurations in combinatorial designs. General design methods and nonconstructive existence theorems to estimate the compaction ratio of an optimal X-compactor are also derived.<br />Comment: 11 pages, final accepted version for publication in the IEEE Transactions on Information Theory
- Subjects :
- Computer Science - Information Theory
Mathematics - Combinatorics
Subjects
Details
- Database :
- arXiv
- Journal :
- IEEE Transactions on Information Theory, 56 (2010) 3196-3206
- Publication Type :
- Report
- Accession number :
- edsarx.1508.00481
- Document Type :
- Working Paper
- Full Text :
- https://doi.org/10.1109/TIT.2010.2048468