MRAM Co-designed Processing-in-Memory CNN Accelerator for Mobile and IoT Applications

We designed a device for Convolution Neural Network applications with non-volatile MRAM memory and computing-in-memory co-designed architecture. It has been successfully fabricated using 22nm technology node CMOS Si process. More than 40MB MRAM density with 9.9TOPS/W are provided. It enables multiple models within one single chip for mobile and IoT device applications.
Comment: 4 pages, 4 figures, 1 table. Accepted by NIPS 2018 MLPCD workshop