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Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process
- Publication Year :
- 2021
-
Abstract
- Wafer-level performance prediction has been attracting attention to reduce measurement costs without compromising test quality in production tests. Although several efficient methods have been proposed, the site-to-site variation, which is often observed in multi-site testing for radio frequency circuits, has not yet been sufficiently addressed. In this paper, we propose a wafer-level performance prediction method for multi-site testing that can consider the site-to-site variation. The proposed method is based on the Gaussian process, which is widely used for wafer-level spatial correlation modeling, improving the prediction accuracy by extending hierarchical modeling to exploit the test site information provided by test engineers. In addition, we propose an active test-site sampling method to maximize measurement cost reduction. Through experiments using industrial production test data, we demonstrate that the proposed method can reduce the estimation error to 1/19 of that obtained using a conventional method. Moreover, we demonstrate that the proposed sampling method can reduce the number of the measurements by 97% while achieving sufficient estimation accuracy.<br />Comment: 10 pages, 13 figures
- Subjects :
- Computer Science - Hardware Architecture
Subjects
Details
- Database :
- arXiv
- Publication Type :
- Report
- Accession number :
- edsarx.2111.01369
- Document Type :
- Working Paper