Reuse Detector: Improving the Management of STT-RAM SLLCs

Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently postulated as the prime contender due to its better energy efficiency, smaller die footprint and higher scalability. However, STT-RAM also exhibits some drawbacks, like slow and energy-hungry write operations, that need to be mitigated. In this work we address these shortcomings by leveraging a new management mechanism for STT-RAM SLLCs. This approach is based on the previous observation that the stream of references arriving at the SLLC of a Chip MultiProcessor (CMP) exhibits reuse locality, i.e., those blocks referenced several times manifest high probability of forthcoming reuse. In this paper, we employ a cache management mechanism that selects the contents of the SLLC aimed to exploit reuse locality instead of temporal locality. Specifically, our proposal consists in the inclusion of a Reuse Detector between private cache levels and the STT-RAM SLLC to detect blocks that do not exhibit reuse, in order to avoid their insertion in the SLLC, hence reducing the number of write operations and the energy consumption in the STT-RAM. Our evaluation reveals that our scheme reports on average, energy reductions in the SLLC in the range of 37-30\%, additional energy savings in the main memory in the range of 6-8\% and performance improvements of 3\% up to 14\% (16-core) compared to an STT-RAM SLLC baseline where no reuse detector is employed. More importantly, our approach outperforms DASCA, the state-of-the-art STT-RAM SLLC management, reporting SLLC energy savings in the range of 4-11\% higher than those of DASCA, delivering higher performance in the range of 1.5-14\%, and additional improvements in DRAM energy consumption in the range of 2-9\% higher than DASCA.