Design of an Analog Memory Cell in 0.25 micron CMOS process

MLA

Barai, Paramita. Design of an Analog Memory Cell in 0.25 Micron CMOS Process. 2024. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsarx&AN=edsarx.2402.14822&authtype=sso&custid=ns315887.

APA

Barai, P. (2024). Design of an Analog Memory Cell in 0.25 micron CMOS process.

Chicago

Barai, Paramita. 2024. “Design of an Analog Memory Cell in 0.25 Micron CMOS Process.” http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsarx&AN=edsarx.2402.14822&authtype=sso&custid=ns315887.