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Optimizing Offload Performance in Heterogeneous MPSoCs
- Source :
- 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) Proceedings
- Publication Year :
- 2024
-
Abstract
- Heterogeneous multi-core architectures combine a few "host" cores, optimized for single-thread performance, with many small energy-efficient "accelerator" cores for data-parallel processing, on a single chip. Offloading a computation to the many-core acceleration fabric introduces a communication and synchronization cost which reduces the speedup attainable on the accelerator, particularly for small and fine-grained parallel tasks. We demonstrate that by co-designing the hardware and offload routines, we can increase the speedup of an offloaded DAXPY kernel by as much as 47.9%. Furthermore, we show that it is possible to accurately model the runtime of an offloaded application, accounting for the offload overheads, with as low as 1% MAPE error, enabling optimal offload decisions under offload execution time constraints.<br />Comment: 2 pages, 1 figure. Accepted for publication in the DATE24 conference proceedings
Details
- Database :
- arXiv
- Journal :
- 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) Proceedings
- Publication Type :
- Report
- Accession number :
- edsarx.2404.01908
- Document Type :
- Working Paper