Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC

We present a fault-tolerant by-design RISC-V SoC and experimentally assess it under atmospheric neutrons and 200 MeV protons. The dedicated ECC and Triple-Core Lockstep countermeasures correct most errors, guaranteeing a device cross-section lower than $5.36 \times 10^{-12}$ cm$^2$.
Comment: 4 pages (excluding title page), accepted at RADECS 2024