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A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line
- Source :
- IEEE Access, Vol 11, Pp 30555-30561 (2023)
- Publication Year :
- 2023
- Publisher :
- IEEE, 2023.
-
Abstract
- Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a digital duty-cycle corrector (DCC) with counter-based half-cycle delay line (HCDL) is introduced. The HCDL of conventional edge combiner type DCC requires a large area and make the DCC unsuitable for applications that operate in a wide-range frequency. The proposed counter-based HCDL reduces the silicon cost by repeating the delay line, while maintaining the performance of conventional DCC. A prototype chip fabricated in a 65nm CMOS process has an area of 0.0064mm2 and consumes 2.1mW at 1.6GHz. The measurement results show that the duty-cycle error is less than 0.89% over an input duty-cycle range of 20-80% for 50-1600MHz.
Details
- Language :
- English
- ISSN :
- 21693536
- Volume :
- 11
- Database :
- Directory of Open Access Journals
- Journal :
- IEEE Access
- Publication Type :
- Academic Journal
- Accession number :
- edsdoj.2d870e167b0442a287836ab67c224b72
- Document Type :
- article
- Full Text :
- https://doi.org/10.1109/ACCESS.2023.3262307