Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System

The open-source and customizable features of the RISC-V Instruction Set Architecture (ISA) have facilitated its rapid adoption since its publication in 2011. The availability of numerous free core designs leads to the pervasiveness of RISC-V-based devices on diverse applications spanning the Internet of Things (IoT), embedded systems, artificial intelligence (AI), and virtual/augmented reality (VR/AR). The increasing prevalence of RISC-V cores has consequently caused a demand for high-performance and resource-efficient multicore systems. However, while numerous proposals exist for constructing multicore systems on conventional architectures, realizing an efficient multicore system that effectively leverages the features of RISC-V remains a challenge. This paper introduces a novel hardware/software co-design methodology to address these bottlenecks while minimizing resource utilization. Experimental results demonstrate the efficiency of our approach, exhibiting significant performance gains over single-threaded implementations and even surpassing traditional multi-threaded approaches.