Effects of the grain boundary protrusion position on the off-state current of polycrystalline silicon thin-film transistors

We report the effects of grain boundary (GB) protrusion on the off-state current (IOFF) of p-channel polycrystalline silicon thin-film transistors by using three-dimensional technology computer-aided design (TCAD) simulation. We found that the IOFF at a high drain bias, VDS = −10 V, varies more than 10 times as the position of the GB protrusion changes, whereas it varies less than two times if the GB has no protrusion, i.e. has a flat surface. The TCAD analysis showed that the IOFF was mainly caused by band-to-band tunneling and that it increased noticeably when the GB protrusion was located at a certain distance from the highly doped drain region because the GB protrusion intensified the electric field at the drain junction. We also found that the IOFF increases further when the GB line is not perpendicular to the channel direction but has some tilt angle because the GB protrusion necessarily encompassed a critical region that maximized the electric field when it was positioned within the GB protrusion.