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Efficient field‐programmable gate array‐based reconfigurable accelerator for deep convolution neural network

Authors :
Xianghong Hu
Taosheng Chen
Hongmin Huang
Zihao Liu
Xueming Li
Xiaoming Xiong
Source :
Electronics Letters, Vol 57, Iss 6, Pp 238-240 (2021)
Publication Year :
2021
Publisher :
Wiley, 2021.

Abstract

Abstract Deep convolutional neural networks (DCNNs) have been widely applied in various modern artificial intelligence (AI) applications. DCNN's inference is a process with high calculation costs, which usually requires billions of multiply‐accumulate operations. On mobile platforms such as embedded systems or robotics, an efficient implementation of DCNNs is significant. However, most previous field‐programmable gate array‐based works on accelerators for DCNNs just support one DCNN or just support convolution layers. In order to address this limitation, this work proposes a reconfigurable accelerator. The accelerator is flexible and can support multiple DCNNs and different layer types, such as convolution, pooling, activation function, and full connection layers. It is equipped with a five‐level pipeline convolution engine whose main component is two processing element arrays. Furthermore, a design space exploration method is proposed to make full advantage of the proposed accelerator. This accelerator is implemented with the ZYNQ‐7 ZC706 evaluation board and achieves a high performance of 53.29 Giga operations per second (GOPS) on AlexNet and 45.09 GOPS on YOLOv2‐tiny at 100 MHz. Further performance of the accelerator is compared with the previous works, and it achieves multiple advantages: High performance, high configurability, and efficient resource utilisation.

Details

Language :
English
ISSN :
1350911X and 00135194
Volume :
57
Issue :
6
Database :
Directory of Open Access Journals
Journal :
Electronics Letters
Publication Type :
Academic Journal
Accession number :
edsdoj.70f3c5e289ff46b1bb4002ab7c65b91f
Document Type :
article
Full Text :
https://doi.org/10.1049/ell2.12121