A Novel Current Density Based Design Approach of Low-Noise Amplifiers

The input-referred noise (IRN) is one of the most crucial performance indicators for the analog front-end (AFE) of neural recording devices. In this study, we present a novel design approach for a low-noise amplifier (LNA) based on the transistor optimization method in CMOS technology. Because flicker noise is predominant in neural recording applications, AFE has been designed to meet input-referred flicker noise specifications, whereas thermal noise contributions are monitored and controlled by flicker noise corner frequencies. Transistor optimization is accomplished using a lookup table that encapsulates its performance based on its current density. Initially, transistors are optimized based on the flicker noise performance; later, they may be further optimized based on their size, power consumption, transconductance, or thermal noise contribution. The proposed approach was validated by designing a folded-cascode amplifier with IRN ranging from 2 to 8 $\mu \text{V}_{\text {rms}}$ . The results of the simulation show that the errors of our design methodology are less than 10%, which is less than those of the $g_{m}/I_{D} $ and inversion coefficient methods. The proposed LNA achieves 2.1 $\mu \text{V}_{\text {rms}}$ while consuming 0.83 $\mu \text{W}$ from a 1.2 V supply.