Logic‐in‐Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double‐Gated Feedback Field‐Effect Transistors

MLA

Jaemin Son, et al. “Logic‐in‐Memory Operation of Ternary NAND/NOR Universal Logic Gates Using Double‐Gated Feedback Field‐Effect Transistors.” Advanced Electronic Materials, vol. 9, no. 4, Apr. 2023. EBSCOhost, https://doi.org/10.1002/aelm.202201134.

APA

Jaemin Son, Yunwoo Shin, Kyoungah Cho, & Sangsig Kim. (2023). Logic‐in‐Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double‐Gated Feedback Field‐Effect Transistors. Advanced Electronic Materials, 9(4). https://doi.org/10.1002/aelm.202201134

Chicago

Jaemin Son, Yunwoo Shin, Kyoungah Cho, and Sangsig Kim. 2023. “Logic‐in‐Memory Operation of Ternary NAND/NOR Universal Logic Gates Using Double‐Gated Feedback Field‐Effect Transistors.” Advanced Electronic Materials 9 (4). doi:10.1002/aelm.202201134.