Design of the distributed Cache for reconfigurable array processor

With the increasing number of processor cores integrated on-chip, the problem of “storage walls” in reconfigurable array processors is increasing. Traditionally, the use of multi-level shared Cache hardware design has high complexity and limited parallel access, and it is difficult to meet the memory requirements of reconfigurable array processors. This paper designs a local-priority, global-shared“physical distribution, unified logic” distributed Cache structure. The hardware overhead of this structure is small and parallel access is high. The Xilinx Virtex-6 series xc6vlx550T development board was used to test the design. The experimental results show that the average delay of proposed architecture is reduced by up to 30% compared with the similar structure, and the hardware overhead is only 5% of the Cache capacity. The maximum memory access bandwidth is 10.512 GB/s.