Design and implementation of partial dynamically reconfigurable FPGA process scheduling

In view of the diverse edge computing requirements of the 6G era, reconfigurable technology based on FPGAs can achieve lower latency and provide diversified services. Based on the idea of local dynamic reconfiguration, the ICAP interface is used to reconfigure FPGA resources, so as to realize the local dynamic reconfigurable scheme on the FPGA logic. Drawing on the idea of software process management in the operating system, based on the concept of introducing hardware processes in the Linux operating system, it is possible to divide a whole block of FPGA resources into multiple small FPGA resource blocks, each small reconfigurable FPGA resource block can be abstracted into a hardware process, the hardware process is actually not running on the CPU but running in the FPGA logical resource area, and is only a software language description of the hardware process on the operating system. As a result, the hardware scheme of CPU plus FPGA is designed to achieve partial reconfigurable system, and verified on Xilinx Zynq series chips, and the FPGA hardware resources are scheduled and allocated in a process manner, which greatly improves the utilization and flexibility of FPGA hardware resources.