Back to Search
Start Over
Lumped-circuit model extraction for vias in multilayer substrates
- Source :
- IEEE Transactions on Electromagnetic Compatibility. May, 2003, Vol. 45 Issue 2, p272, 9 p.
- Publication Year :
- 2003
-
Abstract
- Via interconnects in multilayer substrates, such as chip scale packaging, ball grid arrays, multichip modules, and printed circuit boards (PCB) can critically impact system performance. Lumped-circuit models for vias are usually established from their geometries to better understand the physics. This paper presents a procedure to extract these element values from a partial element equivalent circuit type method, denoted by CEMPIE. With a known physics-based circuit prototype, this approach calculates the element values from an extensive circuit net extracted by the CEMPIE method. Via inductances in a PCB power bus, including mutual inductances if multiple vias are present, are extracted in a systematic manner using this approach. A closed-form expression for via self inductance is further derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expression can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power-bus impedance as well as effective frequency range of decoupling capacitors. Index Terms--DC power-bus design, decoupling capacitor design, lumped-circuit model extraction, multilayer substrate, via inductance, via interconnects.
Details
- Language :
- English
- ISSN :
- 00189375
- Volume :
- 45
- Issue :
- 2
- Database :
- Gale General OneFile
- Journal :
- IEEE Transactions on Electromagnetic Compatibility
- Publication Type :
- Academic Journal
- Accession number :
- edsgcl.102841050