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Hardware accelerator speeds mixed-level simulation

Authors :
Tuck, Barbara
Source :
Computer Design. June, 1991, Vol. 30 Issue 9, p118, 2 p.
Publication Year :
1991

Abstract

The XLProcessor (XLP) simulation accelerator from Cadence Design Systems is the hardware implementation of the same XL algorithm that drives the Cadence Verilog-XL and VHDL-XL software simulators. XLP resides in […]

Details

Language :
English
ISSN :
00104566
Volume :
30
Issue :
9
Database :
Gale General OneFile
Journal :
Computer Design
Publication Type :
Academic Journal
Accession number :
edsgcl.10884672