Efficient techniques in the sizing and constrained optimisation of CMOS combinational logic circuits

Subjects

Subjects :

Optimization
Circuit Design
Integrated Circuits
New Technique
CMOS
Combinational Circuits
Logic Circuitry
Algorithm Analysis
Scientific Research

Details

ISSN :

01437062

Volume :

v138

Issue :

n3

Database :

Gale General OneFile

Journal :

IEE Proceedings Part E Computers and Digital Techniques

Publication Type :

Academic Journal

Accession number :

edsgcl.11056753