Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's

Closed-form formulas to model the interconnection delay andvoltage waveform of resistance-capacitance (RC) lines are presented. Such lines are employed as interconnects in very large scale integration circuits and pose a problem due to the capacitive coupling between two lines and the subsequent crosstalk. The expressions are used to determine the optimum width with the least bus RC delay.