Design of low-power fast VCSEL drivers for high-density links in 90-nm SOI CMOS

The continuous decrease of the supply voltage to 1 V and below in CMOS makes the design of laser drivers a challenging task. Hence, a detailed comparison of three basic driver architectures, namely, common source (CS), CS with source degeneration, and source follower (SF) is presented using transistor models including short channel effects. Based on this comparison, two power-optimized driver topologies are implemented in a 90-nm silicon-on-insulator CMOS technology. The SF driver features a bandwidth of 18 GHz on a 50-[ohm] load. The required chip area is only 140 [micro]m x 140 [micro]m, which is very beneficial for high-density short-distance optical interconnects. This allows a data rate of 12.5 Gb/s at a bit error ratio of less than [10.sup.-12] to be achieved even with a 10-Gb/s oxide confined vertical-cavity surface-emitting laser (VCSEL). The power consumption is 27 mW. The drivers were optimized for maximal eye opening by applying a fast and accurate VCSEL model. Index Terms--Common source (CS), modeling, optical interconnects, parasitics, source follower (SF), vertical-cavity surface-emitting laser (VCSEL).