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Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

Authors :
Phatrapornnant, Teera
Pont, Michael J.
Source :
IEEE Transactions on Computers. Feb, 2006, Vol. 55 Issue 2, p113, 12 p.
Publication Year :
2006

Details

Language :
English
ISSN :
00189340
Volume :
55
Issue :
2
Database :
Gale General OneFile
Journal :
IEEE Transactions on Computers
Publication Type :
Academic Journal
Accession number :
edsgcl.144728917