High-performance dual-gate CMOS utilizing a novel self-aligned pocket implantation (SPI) technology

The new self-aligned pocket implantation (SPI) method modifies the MOSFET systems with reduced parasitic junction capacity, thus generating a high-speed circuit activity. The self-aligned gate electrode and TiSi2 film masks embody a local pocket, which is the main characteristic of the SPI system. Reducing the micrometer value to 0.21 micrometer and increasing the drain saturation current of 10% and 20% in N-MOSFET and P-MOSFET are some functions of the SPI system. The SPI MOSFET differs from the LDD MOSFET by reducing the drain junction capacitance in N- and P-MOSFETs. The period of delay of 50 ps and 40 ps in every stage of dual-gate CMOS ring oscillator is effected due to the high current driving efficiency and the low drain junction capacitance.