Laser-induced latchup screening and mitigation in CMOS devices

The application of the pulsed laser approach for identifying latch-up sensitive regions in CMOS circuitry is described. The utility of this approach for preliminary latchup screening of both COTS and space-qualified parts for applications in radiation environments is described. An application of hardening-by-design principles in which a space-qualified CMOS product is modified, based on the pulsed laser results, to be latchup immune, is presented in detail. The design modifications are described. Index Terms--CMOS, laser, latchup, micro-latchup, picosecond, single-event effects, single-event latchup (SEL).