Gate circuit layout optimization of power module regarding transient current imbalance

MLA

Martin, Christian, et al. “Gate Circuit Layout Optimization of Power Module Regarding Transient Current Imbalance.” IEEE Transactions on Power Electronics, vol. 21, no. 5, Sept. 2006, p. 1176. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsggo&AN=edsgcl.152513595&authtype=sso&custid=ns315887.

APA

Martin, C., Guichon, J.-M., Schanen, J.-L., & Pasterczyk, R.-J. (2006). Gate circuit layout optimization of power module regarding transient current imbalance. IEEE Transactions on Power Electronics, 21(5), 1176.

Chicago

Martin, Christian, Jean-Michel Guichon, Jean-Luc Schanen, and Robert-J. Pasterczyk. 2006. “Gate Circuit Layout Optimization of Power Module Regarding Transient Current Imbalance.” IEEE Transactions on Power Electronics 21 (5): 1176. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsggo&AN=edsgcl.152513595&authtype=sso&custid=ns315887.