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Timing models for gallium arsenide direct-coupled FET logic circuits

Authors :
Kayssi, Ayman I.
Sakallah, Karem A.
Source :
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. March, 1995, Vol. v14 Issue n3, p384, 10 p.
Publication Year :
1995

Details

ISSN :
02780070
Volume :
v14
Issue :
n3
Database :
Gale General OneFile
Journal :
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication Type :
Academic Journal
Accession number :
edsgcl.16989901