Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement

Power integrity is a crucial design issue for nano-meter technologies because of decreased supply voltage and increased current. We focused on gate delay variation caused by power/ground noise, and developed a full-chip simulation current model with capacitance and a variable resistor to accurately model current dependency on voltage drop. Measurement results for 90-nm technology are well reproduced in simulation. The error of average supply voltage is 0.9 % in average. Measurement results also demonstrate that gate delay depends on average voltage drop. Index Terms--Delay estimation, full-chip simulation, linear element model, power-supply noise, transistor model.