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Stability and 2-D simulation studies of avalanche breakdown in 4H-SiC DMOSFETs with JTE
- Source :
- IEEE Transactions on Electron Devices. Feb, 2008, Vol. 55 Issue 2, p489, 6 p.
- Publication Year :
- 2008
-
Abstract
- The performance of bias stress induced breakdown voltage (BV) slump measurements on DMOSFETs is discussed. Findings reveal that the BV slumped after the DMOSFET was bias stressed at 1200 V for 2 hours at 175 degree Celsius.
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 55
- Issue :
- 2
- Database :
- Gale General OneFile
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- edsgcl.175060549