A 12-bit ratio-independent algorithmic A/D converter for a capacitive sensor interface

This paper describes a ratio-independent algorithmic analog-digital (A/D) converter architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40-kS/s A/D converter (ADC) with an active die area of 0.041 [mm.sup.2] is implemented in a 0.13-[micro]m CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 68.4-[micro]W power dissipation, the ADC achieves 80.2-dB spurious-free dynamic range and 63.3-dB signal-to-noise and distortion ratio. Index Terms--Accelerometer, algorithmic analog-digital (A/D) converter, low power, ratio independent, sensor.