An evaluation of the CMOS technology roadmap from the point of view of variability, interconnects, and power dissipation

Authors :: Boeuf, Frederic
Sellier, Manuel
Farcy, Alexis
Skotnicki, Thomas
Source :: IEEE Transactions on Electron Devices. June, 2008, Vol. 55 Issue 6, p1433, 8 p.
Publication Year :: 2008
Abstract: A new system-level version of the model for the assessment of complementaryl metal-oxide-semiconductor (CMOS) technologies and roadmaps (MASTAR) model is used for evaluating the International Technology Roadmap for Semiconductors (ITRS) roadmap.

Subjects :: Circuit design -- Analysis
Complementary metal oxide semiconductors -- Models
Static random access memory -- Design and construction
Circuit designer
Integrated circuit design
SRAM
Business
Electronics
Electronics and electrical industries

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