A unifying approach for weighted and diminished-1 modulo [2.sup.n] + 1 addition

In this paper, it is shown that every architecture proposed for modulo [2.sup.n] + 1 addition of operands that follow the diminished-1 representation can also be used in the design of modulo [2.sup.n] + 1 adders for operands that follow the weighted representation. This is achieved by the addition of a constant-time operator composed of a simplified carry-save adder stage. The experimental results indicate that many architectures already proposed for the diminished-1 case, lead to very efficient adders for weighted operands, under this unifying approach. Index Terms--Diminished-1 representation, modulo [2.sup.n] + 1 addition, residue arithmetic, residue number system.