An efficient H.264 intra frame coder system

In this paper, we present an efficient H.264 intra frame coder system that achieves real-time performance for portable consumer electronics applications with low hardware cost. The system includes a low cost intra prediction hardware design that implements all intra prediction modes used in H.264 video coding standard based on a novel organization of the intra prediction equations. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code works at 71 MHz in a Xilinx Virtex II FPGA and it can code 35 CIF (352x288) frames per second. The system also includes software running on an Arm926EJS processor for implementing pre-processing and post-processing functions. The H.264 intra frame coder system is demonstrated to work correctly on an Arm Versatile Platform development board and it is verified to be compliant with H.264 standard. Index Terms--H.264, Video Coding, Intra Frame Coder, Intra Prediction, Hardware Implementation, FPGA.