Vertical InAs nanowire wrap gate transistors on Si substrates

MLA

Rehnstedt, Carl, et al. “Vertical InAs Nanowire Wrap Gate Transistors on Si Substrates.” IEEE Transactions on Electron Devices, vol. 55, no. 11, Nov. 2008, p. 3037. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsggo&AN=edsgcl.192330098&authtype=sso&custid=ns315887.

APA

Rehnstedt, C., Martensson, T., Thelander, C., Samuelson, L., & Wernersson, L.-E. (2008). Vertical InAs nanowire wrap gate transistors on Si substrates. IEEE Transactions on Electron Devices, 55(11), 3037.

Chicago

Rehnstedt, Carl, Thomas Martensson, Claes Thelander, Lars Samuelson, and Lars-Erik Wernersson. 2008. “Vertical InAs Nanowire Wrap Gate Transistors on Si Substrates.” IEEE Transactions on Electron Devices 55 (11): 3037. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsggo&AN=edsgcl.192330098&authtype=sso&custid=ns315887.