A novel biasing technique for addressable parametric arrays

Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that reduces the leakage of these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted almost a two-decade drop in parasitic leakage of the array. Experimental data confirmed this improvement. 1 x 32 and 4 x 32 arrays using this biasing technique were used to investigate probe pad effects, device variability and geometry dependence. Index Terms--MOSFET array, parametric test, probe pads, source biasing, test structure design, variability.