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Leakage current reduction using subthreshold source-coupled logic
- Source :
- IEEE Transactions on Circuits and Systems-II-Express Briefs. May, 2009, Vol. 56 Issue 5, p374, 5 p.
- Publication Year :
- 2009
-
Abstract
- The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low-power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better power--delay performance compared with their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to the lower sensitivity to the process and supply voltage variations, makes the STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer-scale technologies. An analytical approach for comparing the power--delay performance of these two topologies is proposed. Index Terms--CMOS digital circuits, leakage, source-coupled logic (SCL), subthreshold CMOS, subthreshold SCL (STSCL).
- Subjects :
- Complementary metal oxide semiconductors -- Design and construction
Digital integrated circuits -- Design and construction
Circuit design -- Evaluation
Electric currents -- Properties
Electric currents -- Control
Circuit designer
Integrated circuit design
Business
Computers and office automation industries
Electronics
Electronics and electrical industries
Subjects
Details
- Language :
- English
- ISSN :
- 15497747
- Volume :
- 56
- Issue :
- 5
- Database :
- Gale General OneFile
- Journal :
- IEEE Transactions on Circuits and Systems-II-Express Briefs
- Publication Type :
- Academic Journal
- Accession number :
- edsgcl.200915638