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High-performance metal/high-k n- and p-MOSFETs with top-cut dual stress liners using gate-last damascene process on (100) substrates
- Source :
- IEEE Transactions on Electron Devices. April, 2009, Vol. 56 Issue 4, p620, 7 p.
- Publication Year :
- 2009
-
Abstract
- The effects of top-cut stress liners for damascene gate MOSFETs are examined by stress simulation. The results have shown that high channel stress is induced for shorter gate lengths and hence high drive current n- and pFETs are achieved by using top-cut stress liners with dual metal/high-k gates and eSiGe for damascene gate devices.
- Subjects :
- Gates (Electronics) -- Structure
Germanium -- Electric properties
Metal oxide semiconductor field effect transistors -- Evaluation
Silicon alloys -- Mechanical properties
Silicon alloys -- Electric properties
Stress analysis (Engineering) -- Usage
Business
Electronics
Electronics and electrical industries
Subjects
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 56
- Issue :
- 4
- Database :
- Gale General OneFile
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- edsgcl.201761059