Eliminating back-gate bias effects in novel SOI high-voltage device structure

MLA

Xiarong Luo, et al. “Eliminating Back-Gate Bias Effects in Novel SOI High-Voltage Device Structure.” IEEE Transactions on Electron Devices, vol. 56, no. 8, Aug. 2009, p. 1659. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsggo&AN=edsgcl.207027249&authtype=sso&custid=ns315887.

APA

Xiarong Luo, Daping Fu, Lei Lei, Bo Zhang, Zhaoji Li, Shengdong Hu, Zhengyuan Zhang, Zhicheng Feng, & Bin Yan. (2009). Eliminating back-gate bias effects in novel SOI high-voltage device structure. IEEE Transactions on Electron Devices, 56(8), 1659.

Chicago

Xiarong Luo, Daping Fu, Lei Lei, Bo Zhang, Zhaoji Li, Shengdong Hu, Zhengyuan Zhang, Zhicheng Feng, and Bin Yan. 2009. “Eliminating Back-Gate Bias Effects in Novel SOI High-Voltage Device Structure.” IEEE Transactions on Electron Devices 56 (8): 1659. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsggo&AN=edsgcl.207027249&authtype=sso&custid=ns315887.