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High-level test synthesis with hierarchical test generation for delay-fault testability
- Source :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Oct, 2009, Vol. 28 Issue 10, p1583, 14 p.
- Publication Year :
- 2009
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 28
- Issue :
- 10
- Database :
- Gale General OneFile
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Publication Type :
- Academic Journal
- Accession number :
- edsgcl.209454344