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On variable clock methods for path delay testing of sequential circuits
- Source :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Nov, 1997, Vol. v16 Issue n11, p1237, 13 p.
- Publication Year :
- 1997
- Subjects :
- Sequential circuits -- Testing
Delay lines -- Models
Subjects
Details
- ISSN :
- 02780070
- Volume :
- v16
- Issue :
- n11
- Database :
- Gale General OneFile
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Publication Type :
- Academic Journal
- Accession number :
- edsgcl.20998132