VLSI systems design of 51.84 Mb/s transceivers for ATM/LAN and broadband access

System design problems related to the construction of a 51.84 Mb/s asynchronous transfer mode-local area network and broadband access transceivers, and pipelined fractionally spaced linear equalizer architecture were examined. Algorithmic issues such as signal-to-noise ratio and bit-error rate including very-large-scale-integration limitations such as power dissipation, area and speed were examined in a common framework.