0.2-microm fully-self-aligned Y-shaped gate HJFET's with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating

The method used in fabricating a new fully-self-aligned, 0.2-microm, high-aspect ratio, Y-shaped-gate heterojunction-field-effect transistor (HJFET) is presented. Its external gate-fringing capacitance is half of that of existing HJFETs. WSi-collimate sputtering and electroless Au-plating were used in forming the gate electrodes without voids for greater uniformity and reliability. The new HJFET has a small current saturation voltage of 0.25 V, a threshold voltage of 9 mV, a gm(sub max) of 631 mS/mm, an f(sub max) of 120 GHz and a gate-reverse breakdown voltage of -6 V.