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0.2-microm fully-self-aligned Y-shaped gate HJFET's with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating

Authors :
Wada, Shigeki
Tokushima, Masatoshi
Fukaishi, Muneo
Matsuno, Noriaki
Yano, Hitoshi
Hida, Hikaru
Maeda, Tadashi
Source :
IEEE Transactions on Electron Devices. August, 1998, Vol. 45 Issue 8, p1656, 7 p.
Publication Year :
1998

Abstract

The method used in fabricating a new fully-self-aligned, 0.2-microm, high-aspect ratio, Y-shaped-gate heterojunction-field-effect transistor (HJFET) is presented. Its external gate-fringing capacitance is half of that of existing HJFETs. WSi-collimate sputtering and electroless Au-plating were used in forming the gate electrodes without voids for greater uniformity and reliability. The new HJFET has a small current saturation voltage of 0.25 V, a threshold voltage of 9 mV, a gm(sub max) of 631 mS/mm, an f(sub max) of 120 GHz and a gate-reverse breakdown voltage of -6 V.

Details

ISSN :
00189383
Volume :
45
Issue :
8
Database :
Gale General OneFile
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
edsgcl.21094707