Exploiting parity computation latency for on-chip crosstalk reduction

Subjects

Subjects :

Embedded systems -- Design and construction
Error-correcting codes -- Analysis
Noise control -- Methods
Reliability (Engineering) -- Evaluation
Embedded system
System on a chip
Business
Computers and office automation industries
Electronics
Electronics and electrical industries

Details

Language :

English

ISSN :

15497747

Volume :

57

Issue :

5

Database :

Gale General OneFile

Journal :

IEEE Transactions on Circuits and Systems-II-Express Briefs

Publication Type :

Academic Journal

Accession number :

edsgcl.230825926