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An FPGA-based linear all-digital phase-locked loop
- Source :
- IEEE Transactions on Circuits and Systems-I-Regular Papers. Sept, 2010, Vol. 57 Issue 9, p2487, 11 p.
- Publication Year :
- 2010
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 57
- Issue :
- 9
- Database :
- Gale General OneFile
- Journal :
- IEEE Transactions on Circuits and Systems-I-Regular Papers
- Publication Type :
- Academic Journal
- Accession number :
- edsgcl.242720645