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OPTIMIZING PLL Performance Levels; Designing a PLL synthesizer for modern mobile communications systems involves achieving the proper balance among a number of tradeoffs, including spurious levels and frequency switching speed
- Source :
- Microwaves & RF. April 1, 2012, Vol. 51 Issue 4
- Publication Year :
- 2012
-
Abstract
- Byline: SAMIR KAMECHE Assistant Professor MOHAMMED KAMECHE Researcher MOHAMMED FEHAM Professor FREQUENCY SYNTHESIZERS based on phase-locked loops (PLLs) are widely used in radio communications systems. Such signal sources are known [...]
Details
- Language :
- English
- ISSN :
- 07452993
- Volume :
- 51
- Issue :
- 4
- Database :
- Gale General OneFile
- Journal :
- Microwaves & RF
- Publication Type :
- Periodical
- Accession number :
- edsgcl.312429815